A timing Path (TP) is a serial connection of logic elements or cells. An input is made to the TP, and the computation is made as the signal propagates through the TP. The TP delay is of interest in designing a chip: This determines the speed of the chip. The TP delay is the sum of cell delays. Traditional static timing analysis (STA) is, and has been, the method that virtually every digital design team uses to achieve timing signoff. In STA, a timing model is required for every cell in the design, or at least for the signal paths that are analyzed. The analyzer uses those timing models to calculate delays for all cells in a given path. Those delays, in turn, are summed to determine total path delays.
Statistical static timing analysis (SSTA) was developed to account for process variation by using probability distributions. In current implementations, the parameters that vary are typically gate length, gate width, flat-band voltage, oxide thickness and channel doping. These parameters are assumed to vary from one chip to another (global variation), but, within a die, they are assumed to be constant.